1. Field of the Invention
The present invention relates to a reprogrammable combinational circuit wherein an optimization of the signal running time may be realized after the circuit is already programmed.
2. Description of the Prior Art
A commercially available, reprogrammable combinational circuit is typically programmed with a code (bit stream) that determines which individual circuit in the combinational circuit to be programmed. Thus, a nearly arbitrarily prescribable circuit can be programmed into the reprogrammable combinational circuit.
The reprogrammable combinational circuit includes a plurality of cells, wherein each cell contains a combinational block and a register. The combinational blocks, in turn, perform operations corresponding to a prescribable circuit wherein the registers can be switched between a "used" and "unused" state. Accordingly, the registers allow the circuit to become a synchronous circuit, equivalent to a synchronous combinational circuit, dependent on a clock signal.
A person skilled in the art knows that synchronous circuits are those that are based on a common clock and that switch at identical points in time; whether at the positive edge or the negative edge of the clock signal. A definition of synchronous combinational circuit (=synchronous circuit) is provided in H. -J. Schneider, Lexikon der Informatik und Datenverarbeitung, 2.sup.nd Edition, Oldenbourg Verlag, Munich 1986, ISBN 3-486-22662-2, pp. 508, 509.
Combinational blocks lie between registers in the development of synchronous circuits. The signal running time through the combinational blocks as well as setup time and hold time of the registers determine the maximum clock frequency with which the synchronous circuit can be operated.
The maximum clock frequency of a reprogrammable combinational circuit is often inadequate in practice. An enhancement of such performance capability, therefore, would be desirable.